BroadwellMsr.h File Reference

Data Structures
union	MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER
union	MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER
union	MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER
union	MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER

Macros
#define	IS_BROADWELL_PROCESSOR(DisplayFamily, DisplayModel)
#define	MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS   0x0000038E
#define	MSR_BROADWELL_PKG_CST_CONFIG_CONTROL   0x000000E2
#define	MSR_BROADWELL_TURBO_RATIO_LIMIT   0x000001AD
#define	MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT   0x00000620
#define	MSR_BROADWELL_PP0_ENERGY_STATUS   0x00000639

Detailed Description

MSR Definitions for Intel processors based on the Broadwell microarchitecture.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Specification Reference:

Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)

Macro Definition Documentation

#define IS_BROADWELL_PROCESSOR	(		DisplayFamily,
			DisplayModel
	)

Value:

(DisplayFamily == 0x06 && \
   (                        \
    DisplayModel == 0x3D || \
    DisplayModel == 0x47 || \
    DisplayModel == 0x4F || \
    DisplayModel == 0x56    \
    )                       \
   )

Is Intel processors based on the Broadwell microarchitecture?

Parameters

DisplayFamily	Display Family ID
DisplayModel	Display Model ID

Return values

TRUE	Yes, it is.
FALSE	No, it isn't.

#define MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS   0x0000038E

Thread. See Table 2-2. See Section 18.6.2.2, "Global Counter Control Facilities.".

Parameters

ECX	MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS (0x0000038E)
EAX	Lower 32-bits of MSR value. Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.

Example usage

MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS);
AsmWriteMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);

Note

MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.

#define MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT   0x00000620

Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio fields represent the widest possible range of uncore frequencies. Writing to these fields allows software to control the minimum and the maximum frequency that hardware will select.

Parameters

ECX	MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT (0x00000620)
EAX	Lower 32-bits of MSR value. Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.

Example usage

MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT);
AsmWriteMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);

#define MSR_BROADWELL_PKG_CST_CONFIG_CONTROL   0x000000E2

Core. C-State Configuration Control (R/W) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-states. See http://biosbits.org. <http://biosbits.org>__.

Parameters

ECX	MSR_BROADWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)
EAX	Lower 32-bits of MSR value. Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.

Example usage

MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL);
AsmWriteMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);

Note

MSR_BROADWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.

#define MSR_BROADWELL_PP0_ENERGY_STATUS   0x00000639

Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL Domains.".

Parameters

ECX	MSR_BROADWELL_PP0_ENERGY_STATUS (0x00000639)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_BROADWELL_PP0_ENERGY_STATUS);

Note

MSR_BROADWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.

#define MSR_BROADWELL_TURBO_RATIO_LIMIT   0x000001AD

Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, RW if MSR_PLATFORM_INFO.[28] = 1.

Parameters

ECX	MSR_BROADWELL_TURBO_RATIO_LIMIT (0x000001AD)
EAX	Lower 32-bits of MSR value. Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.

Example usage

MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_TURBO_RATIO_LIMIT);

Note

MSR_BROADWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.