Data Structures
union	MSR_ATOM_PLATFORM_ID_REGISTER

union	MSR_ATOM_EBL_CR_POWERON_REGISTER

union	MSR_ATOM_FSB_FREQ_REGISTER

union	MSR_ATOM_BBL_CR_CTL3_REGISTER

union	MSR_ATOM_PERF_STATUS_REGISTER

union	MSR_ATOM_THERM2_CTL_REGISTER

union	MSR_ATOM_IA32_MISC_ENABLE_REGISTER

union	MSR_ATOM_PEBS_ENABLE_REGISTER

Macros
#define	IS_ATOM_PROCESSOR(DisplayFamily, DisplayModel)

#define	MSR_ATOM_PLATFORM_ID 0x00000017

#define	MSR_ATOM_EBL_CR_POWERON 0x0000002A

#define	MSR_ATOM_FSB_FREQ 0x000000CD

#define	MSR_ATOM_BBL_CR_CTL3 0x0000011E

#define	MSR_ATOM_PERF_STATUS 0x00000198

#define	MSR_ATOM_THERM2_CTL 0x0000019D

#define	MSR_ATOM_IA32_MISC_ENABLE 0x000001A0

#define	MSR_ATOM_LASTBRANCH_TOS 0x000001C9

#define	MSR_ATOM_LER_FROM_LIP 0x000001DD

#define	MSR_ATOM_LER_TO_LIP 0x000001DE

#define	MSR_ATOM_PEBS_ENABLE 0x000003F1

#define	MSR_ATOM_PKG_C2_RESIDENCY 0x000003F8

#define	MSR_ATOM_PKG_C4_RESIDENCY 0x000003F9

#define	MSR_ATOM_PKG_C6_RESIDENCY 0x000003FA


#define	MSR_ATOM_LASTBRANCH_0_FROM_IP 0x00000040

#define	MSR_ATOM_LASTBRANCH_1_FROM_IP 0x00000041

#define	MSR_ATOM_LASTBRANCH_2_FROM_IP 0x00000042

#define	MSR_ATOM_LASTBRANCH_3_FROM_IP 0x00000043

#define	MSR_ATOM_LASTBRANCH_4_FROM_IP 0x00000044

#define	MSR_ATOM_LASTBRANCH_5_FROM_IP 0x00000045

#define	MSR_ATOM_LASTBRANCH_6_FROM_IP 0x00000046

#define	MSR_ATOM_LASTBRANCH_7_FROM_IP 0x00000047


#define	MSR_ATOM_LASTBRANCH_0_TO_IP 0x00000060

#define	MSR_ATOM_LASTBRANCH_1_TO_IP 0x00000061

#define	MSR_ATOM_LASTBRANCH_2_TO_IP 0x00000062

#define	MSR_ATOM_LASTBRANCH_3_TO_IP 0x00000063

#define	MSR_ATOM_LASTBRANCH_4_TO_IP 0x00000064

#define	MSR_ATOM_LASTBRANCH_5_TO_IP 0x00000065

#define	MSR_ATOM_LASTBRANCH_6_TO_IP 0x00000066

#define	MSR_ATOM_LASTBRANCH_7_TO_IP 0x00000067

Detailed Description

MSR Definitions for the Intel(R) Atom(TM) Processor Family.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Specification Reference:: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)

Macro Definition Documentation

#define IS_ATOM_PROCESSOR	(	DisplayFamily,
		DisplayModel
	)

Value:

(DisplayFamily == 0x06 && \
   (                        \
    DisplayModel == 0x1C || \
    DisplayModel == 0x26 || \
    DisplayModel == 0x27 || \
    DisplayModel == 0x35 || \
    DisplayModel == 0x36    \
    )                       \
   )

Is Intel(R) Atom(TM) Processor Family?

Parameters

DisplayFamily	Display Family ID
DisplayModel	Display Model ID

Return values

TRUE	Yes, it is.
FALSE	No, it isn't.

#define MSR_ATOM_BBL_CR_CTL3 0x0000011E

Shared.

Parameters

ECX	MSR_ATOM_BBL_CR_CTL3 (0x0000011E)
EAX	Lower 32-bits of MSR value. Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER.

Example usage

MSR_ATOM_BBL_CR_CTL3_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_BBL_CR_CTL3);
AsmWriteMsr64 (MSR_ATOM_BBL_CR_CTL3, Msr.Uint64);

Note: MSR_ATOM_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.

#define MSR_ATOM_EBL_CR_POWERON 0x0000002A

Shared. Processor Hard Power-On Configuration (R/W) Enables and disables processor features; (R) indicates current processor configuration.

Parameters

ECX	MSR_ATOM_EBL_CR_POWERON (0x0000002A)
EAX	Lower 32-bits of MSR value. Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.

Example usage

MSR_ATOM_EBL_CR_POWERON_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_EBL_CR_POWERON);
AsmWriteMsr64 (MSR_ATOM_EBL_CR_POWERON, Msr.Uint64);

Note: MSR_ATOM_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.

#define MSR_ATOM_FSB_FREQ 0x000000CD

Shared. Scalable Bus Speed(RO) This field indicates the intended scalable bus clock speed for processors based on Intel Atom microarchitecture:.

Parameters

ECX	MSR_ATOM_FSB_FREQ (0x000000CD)
EAX	Lower 32-bits of MSR value. Described by the type MSR_ATOM_FSB_FREQ_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_ATOM_FSB_FREQ_REGISTER.

Example usage

MSR_ATOM_FSB_FREQ_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_FSB_FREQ);

Note: MSR_ATOM_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.

#define MSR_ATOM_IA32_MISC_ENABLE 0x000001A0

Unique. Enable Misc. Processor Features (R/W) Allows a variety of processor functions to be enabled and disabled.

Parameters

ECX	MSR_ATOM_IA32_MISC_ENABLE (0x000001A0)
EAX	Lower 32-bits of MSR value. Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER.

Example usage

MSR_ATOM_IA32_MISC_ENABLE_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_IA32_MISC_ENABLE);
AsmWriteMsr64 (MSR_ATOM_IA32_MISC_ENABLE, Msr.Uint64);

Note: MSR_ATOM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.

#define MSR_ATOM_LASTBRANCH_0_FROM_IP 0x00000040

Unique. Last Branch Record n From IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.5.

Parameters

ECX	MSR_ATOM_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_ATOM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.

#define MSR_ATOM_LASTBRANCH_0_TO_IP 0x00000060

Unique. Last Branch Record n To IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the destination instruction.

Parameters

ECX	MSR_ATOM_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_ATOM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_ATOM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_ATOM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_ATOM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_ATOM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_ATOM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_ATOM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_ATOM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.

#define MSR_ATOM_LASTBRANCH_1_FROM_IP 0x00000041

Unique. Last Branch Record n From IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.5.

Parameters

ECX	MSR_ATOM_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_ATOM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.

#define MSR_ATOM_LASTBRANCH_1_TO_IP 0x00000061

Unique. Last Branch Record n To IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the destination instruction.

Parameters

ECX	MSR_ATOM_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_ATOM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_ATOM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_ATOM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_ATOM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_ATOM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_ATOM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_ATOM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_ATOM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.

#define MSR_ATOM_LASTBRANCH_2_FROM_IP 0x00000042

Unique. Last Branch Record n From IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.5.

Parameters

ECX	MSR_ATOM_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_ATOM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.

#define MSR_ATOM_LASTBRANCH_2_TO_IP 0x00000062

Unique. Last Branch Record n To IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the destination instruction.

Parameters

ECX	MSR_ATOM_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_ATOM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_ATOM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_ATOM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_ATOM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_ATOM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_ATOM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_ATOM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_ATOM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.

#define MSR_ATOM_LASTBRANCH_3_FROM_IP 0x00000043

Unique. Last Branch Record n From IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.5.

Parameters

ECX	MSR_ATOM_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_ATOM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.

#define MSR_ATOM_LASTBRANCH_3_TO_IP 0x00000063

Unique. Last Branch Record n To IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the destination instruction.

Parameters

ECX	MSR_ATOM_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_ATOM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_ATOM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_ATOM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_ATOM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_ATOM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_ATOM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_ATOM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_ATOM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.

#define MSR_ATOM_LASTBRANCH_4_FROM_IP 0x00000044

Unique. Last Branch Record n From IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.5.

Parameters

ECX	MSR_ATOM_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_ATOM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.

#define MSR_ATOM_LASTBRANCH_4_TO_IP 0x00000064

Unique. Last Branch Record n To IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the destination instruction.

Parameters

ECX	MSR_ATOM_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_ATOM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_ATOM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_ATOM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_ATOM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_ATOM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_ATOM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_ATOM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_ATOM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.

#define MSR_ATOM_LASTBRANCH_5_FROM_IP 0x00000045

Unique. Last Branch Record n From IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.5.

Parameters

ECX	MSR_ATOM_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_ATOM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.

#define MSR_ATOM_LASTBRANCH_5_TO_IP 0x00000065

Unique. Last Branch Record n To IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the destination instruction.

Parameters

ECX	MSR_ATOM_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_ATOM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_ATOM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_ATOM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_ATOM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_ATOM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_ATOM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_ATOM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_ATOM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.

#define MSR_ATOM_LASTBRANCH_6_FROM_IP 0x00000046

Unique. Last Branch Record n From IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.5.

Parameters

ECX	MSR_ATOM_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_ATOM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.

#define MSR_ATOM_LASTBRANCH_6_TO_IP 0x00000066

Unique. Last Branch Record n To IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the destination instruction.

Parameters

ECX	MSR_ATOM_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_ATOM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_ATOM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_ATOM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_ATOM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_ATOM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_ATOM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_ATOM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_ATOM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.

#define MSR_ATOM_LASTBRANCH_7_FROM_IP 0x00000047

Unique. Last Branch Record n From IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.5.

Parameters

ECX	MSR_ATOM_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_ATOM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_ATOM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.

#define MSR_ATOM_LASTBRANCH_7_TO_IP 0x00000067

Unique. Last Branch Record n To IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the destination instruction.

Parameters

ECX	MSR_ATOM_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_ATOM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_ATOM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_ATOM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_ATOM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_ATOM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_ATOM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_ATOM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_ATOM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.

#define MSR_ATOM_LASTBRANCH_TOS 0x000001C9

Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2) that points to the MSR containing the most recent branch record. See MSR_LASTBRANCH_0_FROM_IP (at 40H).

Parameters

ECX	MSR_ATOM_LASTBRANCH_TOS (0x000001C9)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_TOS);
AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_TOS, Msr);

Note: MSR_ATOM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.

#define MSR_ATOM_LER_FROM_LIP 0x000001DD

Unique. Last Exception Record From Linear IP (R) Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled.

Parameters

ECX	MSR_ATOM_LER_FROM_LIP (0x000001DD)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_ATOM_LER_FROM_LIP);

Note: MSR_ATOM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.

#define MSR_ATOM_LER_TO_LIP 0x000001DE

Unique. Last Exception Record To Linear IP (R) This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled.

Parameters

ECX	MSR_ATOM_LER_TO_LIP (0x000001DE)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_ATOM_LER_TO_LIP);

Note: MSR_ATOM_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.

#define MSR_ATOM_PEBS_ENABLE 0x000003F1

Unique. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling (PEBS).".

Parameters

ECX	MSR_ATOM_PEBS_ENABLE (0x000003F1)
EAX	Lower 32-bits of MSR value. Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER.

Example usage

MSR_ATOM_PEBS_ENABLE_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PEBS_ENABLE);
AsmWriteMsr64 (MSR_ATOM_PEBS_ENABLE, Msr.Uint64);

Note: MSR_ATOM_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.

#define MSR_ATOM_PERF_STATUS 0x00000198

Shared.

Parameters

ECX	MSR_ATOM_PERF_STATUS (0x00000198)
EAX	Lower 32-bits of MSR value. Described by the type MSR_ATOM_PERF_STATUS_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_ATOM_PERF_STATUS_REGISTER.

Example usage

MSR_ATOM_PERF_STATUS_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PERF_STATUS);
AsmWriteMsr64 (MSR_ATOM_PERF_STATUS, Msr.Uint64);

Note: MSR_ATOM_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.

#define MSR_ATOM_PKG_C2_RESIDENCY 0x000003F8

Package. Package C2 Residency Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. Package. Package C2 Residency Counter. (R/O) Time that this package is in processor-specific C2 states since last reset. Counts at 1 Mhz frequency.

Parameters

ECX	MSR_ATOM_PKG_C2_RESIDENCY (0x000003F8)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_ATOM_PKG_C2_RESIDENCY);
AsmWriteMsr64 (MSR_ATOM_PKG_C2_RESIDENCY, Msr);

Note: MSR_ATOM_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.

#define MSR_ATOM_PKG_C4_RESIDENCY 0x000003F9

Package. Package C4 Residency Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. Package. Package C4 Residency Counter. (R/O) Time that this package is in processor-specific C4 states since last reset. Counts at 1 Mhz frequency.

Parameters

ECX	MSR_ATOM_PKG_C4_RESIDENCY (0x000003F9)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_ATOM_PKG_C4_RESIDENCY);
AsmWriteMsr64 (MSR_ATOM_PKG_C4_RESIDENCY, Msr);

Note: MSR_ATOM_PKG_C4_RESIDENCY is defined as MSR_PKG_C4_RESIDENCY in SDM.

#define MSR_ATOM_PKG_C6_RESIDENCY 0x000003FA

Package. Package C6 Residency Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. Package. Package C6 Residency Counter. (R/O) Time that this package is in processor-specific C6 states since last reset. Counts at 1 Mhz frequency.

Parameters

ECX	MSR_ATOM_PKG_C6_RESIDENCY (0x000003FA)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_ATOM_PKG_C6_RESIDENCY);
AsmWriteMsr64 (MSR_ATOM_PKG_C6_RESIDENCY, Msr);

Note: MSR_ATOM_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.

#define MSR_ATOM_PLATFORM_ID 0x00000017

Shared. Model Specific Platform ID (R).

Parameters

ECX	MSR_ATOM_PLATFORM_ID (0x00000017)
EAX	Lower 32-bits of MSR value. Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.

Example usage

MSR_ATOM_PLATFORM_ID_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PLATFORM_ID);

Note: MSR_ATOM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.

#define MSR_ATOM_THERM2_CTL 0x0000019D

Shared.

Parameters

ECX	MSR_ATOM_THERM2_CTL (0x0000019D)
EAX	Lower 32-bits of MSR value. Described by the type MSR_ATOM_THERM2_CTL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_ATOM_THERM2_CTL_REGISTER.

Example usage

MSR_ATOM_THERM2_CTL_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_THERM2_CTL);
AsmWriteMsr64 (MSR_ATOM_THERM2_CTL, Msr.Uint64);

Note: MSR_ATOM_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.

Data Structures

Macros

Detailed Description

Macro Definition Documentation