Data Structures
union	HPET_GENERAL_CAPABILITIES_ID_REGISTER

union	HPET_GENERAL_CONFIGURATION_REGISTER

union	HPET_TIMER_CONFIGURATION_REGISTER

union	HPET_TIMER_MSI_ROUTE_REGISTER

Macros
#define	HPET_GENERAL_CAPABILITIES_ID_OFFSET 0x000

#define	HPET_GENERAL_CONFIGURATION_OFFSET 0x010

#define	HPET_GENERAL_INTERRUPT_STATUS_OFFSET 0x020

#define	HPET_MAIN_COUNTER_OFFSET 0x0F0

#define	HPET_TIMER_CONFIGURATION_OFFSET 0x100

#define	HPET_TIMER_COMPARATOR_OFFSET 0x108

#define	HPET_TIMER_MSI_ROUTE_OFFSET 0x110

#define	HPET_TIMER_STRIDE 0x20

Detailed Description

HPET register definitions from the IA-PC HPET (High Precision Event Timers) Specification, Revision 1.0a, October 2004.

Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Macro Definition Documentation

#define HPET_GENERAL_CAPABILITIES_ID_OFFSET 0x000

HPET General Register Offsets

#define HPET_GENERAL_CONFIGURATION_OFFSET 0x010

#define HPET_GENERAL_INTERRUPT_STATUS_OFFSET 0x020

#define HPET_MAIN_COUNTER_OFFSET 0x0F0

HPET Timer Register Offsets

#define HPET_TIMER_COMPARATOR_OFFSET 0x108

#define HPET_TIMER_CONFIGURATION_OFFSET 0x100

#define HPET_TIMER_MSI_ROUTE_OFFSET 0x110

#define HPET_TIMER_STRIDE 0x20

Stride between sets of HPET Timer Registers