OvmfPkg[all]
0.1
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Public Member Functions | |
__DECL_REG (x0, r0_usr) | |
__DECL_REG (x1, r1_usr) | |
__DECL_REG (x2, r2_usr) | |
__DECL_REG (x3, r3_usr) | |
__DECL_REG (x4, r4_usr) | |
__DECL_REG (x5, r5_usr) | |
__DECL_REG (x6, r6_usr) | |
__DECL_REG (x7, r7_usr) | |
__DECL_REG (x8, r8_usr) | |
__DECL_REG (x9, r9_usr) | |
__DECL_REG (x10, r10_usr) | |
__DECL_REG (x11, r11_usr) | |
__DECL_REG (x12, r12_usr) | |
__DECL_REG (x13, sp_usr) | |
__DECL_REG (x14, lr_usr) | |
__DECL_REG (x15, __unused_sp_hyp) | |
__DECL_REG (x16, lr_irq) | |
__DECL_REG (x17, sp_irq) | |
__DECL_REG (x18, lr_svc) | |
__DECL_REG (x19, sp_svc) | |
__DECL_REG (x20, lr_abt) | |
__DECL_REG (x21, sp_abt) | |
__DECL_REG (x22, lr_und) | |
__DECL_REG (x23, sp_und) | |
__DECL_REG (x24, r8_fiq) | |
__DECL_REG (x25, r9_fiq) | |
__DECL_REG (x26, r10_fiq) | |
__DECL_REG (x27, r11_fiq) | |
__DECL_REG (x28, r12_fiq) | |
__DECL_REG (x29, sp_fiq) | |
__DECL_REG (x30, lr_fiq) | |
__DECL_REG (pc64, pc32) | |
Data Fields | |
UINT32 | cpsr |
union { | |
UINT32 spsr_el1 | |
UINT32 spsr_svc | |
}; | |
UINT32 | spsr_fiq |
UINT32 | spsr_irq |
UINT32 | spsr_und |
UINT32 | spsr_abt |
UINT64 | sp_el0 |
UINT64 | sp_el1 |
UINT64 | elr_el1 |
vcpu_guest_core_regs::__DECL_REG | ( | x0 | , |
r0_usr | |||
) |
vcpu_guest_core_regs::__DECL_REG | ( | x1 | , |
r1_usr | |||
) |
vcpu_guest_core_regs::__DECL_REG | ( | x2 | , |
r2_usr | |||
) |
vcpu_guest_core_regs::__DECL_REG | ( | x3 | , |
r3_usr | |||
) |
vcpu_guest_core_regs::__DECL_REG | ( | x4 | , |
r4_usr | |||
) |
vcpu_guest_core_regs::__DECL_REG | ( | x5 | , |
r5_usr | |||
) |
vcpu_guest_core_regs::__DECL_REG | ( | x6 | , |
r6_usr | |||
) |
vcpu_guest_core_regs::__DECL_REG | ( | x7 | , |
r7_usr | |||
) |
vcpu_guest_core_regs::__DECL_REG | ( | x8 | , |
r8_usr | |||
) |
vcpu_guest_core_regs::__DECL_REG | ( | x9 | , |
r9_usr | |||
) |
vcpu_guest_core_regs::__DECL_REG | ( | x10 | , |
r10_usr | |||
) |
vcpu_guest_core_regs::__DECL_REG | ( | x11 | , |
r11_usr | |||
) |
vcpu_guest_core_regs::__DECL_REG | ( | x12 | , |
r12_usr | |||
) |
vcpu_guest_core_regs::__DECL_REG | ( | x13 | , |
sp_usr | |||
) |
vcpu_guest_core_regs::__DECL_REG | ( | x14 | , |
lr_usr | |||
) |
vcpu_guest_core_regs::__DECL_REG | ( | x15 | , |
__unused_sp_hyp | |||
) |
vcpu_guest_core_regs::__DECL_REG | ( | x16 | , |
lr_irq | |||
) |
vcpu_guest_core_regs::__DECL_REG | ( | x17 | , |
sp_irq | |||
) |
vcpu_guest_core_regs::__DECL_REG | ( | x18 | , |
lr_svc | |||
) |
vcpu_guest_core_regs::__DECL_REG | ( | x19 | , |
sp_svc | |||
) |
vcpu_guest_core_regs::__DECL_REG | ( | x20 | , |
lr_abt | |||
) |
vcpu_guest_core_regs::__DECL_REG | ( | x21 | , |
sp_abt | |||
) |
vcpu_guest_core_regs::__DECL_REG | ( | x22 | , |
lr_und | |||
) |
vcpu_guest_core_regs::__DECL_REG | ( | x23 | , |
sp_und | |||
) |
vcpu_guest_core_regs::__DECL_REG | ( | x24 | , |
r8_fiq | |||
) |
vcpu_guest_core_regs::__DECL_REG | ( | x25 | , |
r9_fiq | |||
) |
vcpu_guest_core_regs::__DECL_REG | ( | x26 | , |
r10_fiq | |||
) |
vcpu_guest_core_regs::__DECL_REG | ( | x27 | , |
r11_fiq | |||
) |
vcpu_guest_core_regs::__DECL_REG | ( | x28 | , |
r12_fiq | |||
) |
vcpu_guest_core_regs::__DECL_REG | ( | x29 | , |
sp_fiq | |||
) |
vcpu_guest_core_regs::__DECL_REG | ( | x30 | , |
lr_fiq | |||
) |
vcpu_guest_core_regs::__DECL_REG | ( | pc64 | , |
pc32 | |||
) |
union { ... } |
UINT32 vcpu_guest_core_regs::cpsr |
UINT64 vcpu_guest_core_regs::elr_el1 |
UINT64 vcpu_guest_core_regs::sp_el0 |
UINT64 vcpu_guest_core_regs::sp_el1 |
UINT32 vcpu_guest_core_regs::spsr_abt |
UINT32 vcpu_guest_core_regs::spsr_el1 |
UINT32 vcpu_guest_core_regs::spsr_fiq |
UINT32 vcpu_guest_core_regs::spsr_irq |
UINT32 vcpu_guest_core_regs::spsr_svc |
UINT32 vcpu_guest_core_regs::spsr_und |