TpmTis.h File Reference

Data Structures
struct	TIS_PC_REGISTERS

Macros
#define	TIS_PC_VALID   BIT7
#define	TIS_PC_ACC_ACTIVE   BIT5
#define	TIS_PC_ACC_SEIZED   BIT4
#define	TIS_PC_ACC_SEIZE   BIT3
#define	TIS_PC_ACC_PENDIND   BIT2
#define	TIS_PC_ACC_RQUUSE   BIT1
#define	TIS_PC_ACC_ESTABLISH   BIT0
#define	TIS_PC_STS_CANCEL   BIT24
#define	TIS_PC_STS_VALID   BIT7
#define	TIS_PC_STS_READY   BIT6
#define	TIS_PC_STS_GO   BIT5
#define	TIS_PC_STS_DATA   BIT4
#define	TIS_PC_STS_EXPECT   BIT3
#define	TIS_PC_STS_SELFTEST_DONE   BIT2
#define	TIS_PC_STS_RETRY   BIT1
#define	TIS_TIMEOUT_A   (750 * 1000)
#define	TIS_TIMEOUT_B   (2000 * 1000)
#define	TIS_TIMEOUT_C   (750 * 1000)
#define	TIS_TIMEOUT_D   (750 * 1000)

Typedefs
typedef TIS_PC_REGISTERS *	TIS_PC_REGISTERS_PTR

Detailed Description

TPM Interface Specification definition. It covers both TPM1.2 and TPM2.0.

Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Macro Definition Documentation

#define TIS_PC_ACC_ACTIVE   BIT5

Indicate that this locality is active.

#define TIS_PC_ACC_ESTABLISH   BIT0

A value of 1 indicates that a T/OS has not been established on the platform

#define TIS_PC_ACC_PENDIND   BIT2

When this bit is 1, another locality is requesting usage of the TPM.

#define TIS_PC_ACC_RQUUSE   BIT1

Set to 1 to indicate that this locality is requesting to use TPM.

#define TIS_PC_ACC_SEIZE   BIT3

Set to 1 to indicate that TPM MUST reset the TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the locality that is writing this bit.

#define TIS_PC_ACC_SEIZED   BIT4

Set to 1 to indicate that this locality had the TPM taken away while this locality had the TIS_PC_ACC_ACTIVE bit set.

#define TIS_PC_STS_CANCEL   BIT24

Write a 1 to this bit to notify TPM to cancel currently executing command

#define TIS_PC_STS_DATA   BIT4

This bit indicates that the TPM has data available as a response.

#define TIS_PC_STS_EXPECT   BIT3

The TPM sets this bit to a value of 1 when it expects another byte of data for a command.

#define TIS_PC_STS_GO   BIT5

Write a 1 to this bit to cause the TPM to execute that command.

#define TIS_PC_STS_READY   BIT6

When this bit is 1, TPM is in the Ready state, indicating it is ready to receive a new command.

#define TIS_PC_STS_RETRY   BIT1

Writes a 1 to this bit to force the TPM to re-send the response.

#define TIS_PC_STS_SELFTEST_DONE   BIT2

Indicates that the TPM has completed all self-test actions following a TPM_ContinueSelfTest command.

#define TIS_PC_STS_VALID   BIT7

This field indicates that STS_DATA and STS_EXPECT are valid

#define TIS_PC_VALID   BIT7

This bit is a 1 to indicate that the other bits in this register are valid.

#define TIS_TIMEOUT_A   (750 * 1000)

#define TIS_TIMEOUT_B   (2000 * 1000)

#define TIS_TIMEOUT_C   (750 * 1000)

#define TIS_TIMEOUT_D   (750 * 1000)

Typedef Documentation

typedef TIS_PC_REGISTERS* TIS_PC_REGISTERS_PTR