PciExpress50.h File Reference

Data Structures
union	PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES
union	PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL
union	PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS
union	PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1
union	PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2
union	PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1
union	PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2
union	PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL
struct	PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_32_0

Macros
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_32_0_ID   0x002A
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_32_0_VER1   0x1
#define	PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES_OFFSET   0x04
#define	PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL_OFFSET   0x08
#define	PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS_OFFSET   0x0C
#define	PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1_OFFSET   0x10
#define	PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2_OFFSET   0x14
#define	PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1_OFFSET   0x18
#define	PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2_OFFSET   0x1C
#define	PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL_OFFSET   0x20

Detailed Description

Support for the PCI Express 5.0 standard.

This header file may not define all structures. Please extend as required.

Copyright (c) 2020, American Megatrends International LLC. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Macro Definition Documentation

#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_32_0_ID   0x002A

The Physical Layer PCI Express Extended Capability definitions.

Based on section 7.7.6 of PCI Express Base Specification 5.0.

#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_32_0_VER1   0x1

The Physical Layer PCI Express Extended Capability definitions.

Based on section 7.7.6 of PCI Express Base Specification 5.0.

#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES_OFFSET   0x04

The Physical Layer PCI Express Extended Capability definitions.

Based on section 7.7.6 of PCI Express Base Specification 5.0.

#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL_OFFSET   0x08

The Physical Layer PCI Express Extended Capability definitions.

Based on section 7.7.6 of PCI Express Base Specification 5.0.

#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL_OFFSET   0x20

The Physical Layer PCI Express Extended Capability definitions.

Based on section 7.7.6 of PCI Express Base Specification 5.0.

#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1_OFFSET   0x10

The Physical Layer PCI Express Extended Capability definitions.

Based on section 7.7.6 of PCI Express Base Specification 5.0.

#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2_OFFSET   0x14

The Physical Layer PCI Express Extended Capability definitions.

Based on section 7.7.6 of PCI Express Base Specification 5.0.

#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS_OFFSET   0x0C

The Physical Layer PCI Express Extended Capability definitions.

Based on section 7.7.6 of PCI Express Base Specification 5.0.

#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1_OFFSET   0x18

The Physical Layer PCI Express Extended Capability definitions.

Based on section 7.7.6 of PCI Express Base Specification 5.0.

#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2_OFFSET   0x1C

The Physical Layer PCI Express Extended Capability definitions.

Based on section 7.7.6 of PCI Express Base Specification 5.0.