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ArmPkg[all]
0.1
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Defines the structure of the CSSELR (Cache Size Selection) register. More...
Data Fields | |
| struct { | |
| UINT32 InD:1 | |
| Instruction not Data bit. More... | |
| UINT32 Level:3 | |
| Cache level (zero based) More... | |
| UINT32 TnD:1 | |
| Allocation not Data bit. More... | |
| UINT32 Reserved:27 | |
| Reserved, RES0. More... | |
| } | Bits |
| Bitfield definition of the register. More... | |
| UINT32 | Data |
| The entire 32-bit value. More... | |
Defines the structure of the CSSELR (Cache Size Selection) register.
| struct { ... } CSSELR_DATA::Bits |
Bitfield definition of the register.
| UINT32 CSSELR_DATA::Data |
The entire 32-bit value.
| UINT32 CSSELR_DATA::InD |
Instruction not Data bit.
| UINT32 CSSELR_DATA::Level |
Cache level (zero based)
| UINT32 CSSELR_DATA::Reserved |
Reserved, RES0.
| UINT32 CSSELR_DATA::TnD |
Allocation not Data bit.