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ArmLib.h File Reference

Data Structures

struct  ARM_MEMORY_REGION_DESCRIPTOR
 

Macros

#define EFI_MEMORY_CACHETYPE_MASK
 
#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr)   ((UINT32)(attr) & 1)
 
#define ARM_CPU_IMPLEMENTER_MASK   (0xFFU << 24)
 
#define ARM_CPU_IMPLEMENTER_ARMLTD   (0x41U << 24)
 
#define ARM_CPU_IMPLEMENTER_DEC   (0x44U << 24)
 
#define ARM_CPU_IMPLEMENTER_MOT   (0x4DU << 24)
 
#define ARM_CPU_IMPLEMENTER_QUALCOMM   (0x51U << 24)
 
#define ARM_CPU_IMPLEMENTER_MARVELL   (0x56U << 24)
 
#define ARM_CPU_PRIMARY_PART_MASK   (0xFFF << 4)
 
#define ARM_CPU_PRIMARY_PART_CORTEXA5   (0xC05 << 4)
 
#define ARM_CPU_PRIMARY_PART_CORTEXA7   (0xC07 << 4)
 
#define ARM_CPU_PRIMARY_PART_CORTEXA8   (0xC08 << 4)
 
#define ARM_CPU_PRIMARY_PART_CORTEXA9   (0xC09 << 4)
 
#define ARM_CPU_PRIMARY_PART_CORTEXA15   (0xC0F << 4)
 
#define ARM_CORE_AFF0   0xFF
 
#define ARM_CORE_AFF1   (0xFF << 8)
 
#define ARM_CORE_AFF2   (0xFF << 16)
 
#define ARM_CORE_AFF3   (0xFFULL << 32)
 
#define ARM_CORE_MASK   ARM_CORE_AFF0
 
#define ARM_CLUSTER_MASK   ARM_CORE_AFF1
 
#define GET_CORE_ID(MpId)   ((MpId) & ARM_CORE_MASK)
 
#define GET_CLUSTER_ID(MpId)   (((MpId) & ARM_CLUSTER_MASK) >> 8)
 
#define GET_MPID(ClusterId, CoreId)   (((ClusterId) << 8) | (CoreId))
 
#define PRIMARY_CORE_ID   (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
 
#define ARM_ARCH_TIMER_ENABLE   (1 << 0)
 
#define ARM_ARCH_TIMER_IMASK   (1 << 1)
 
#define ARM_ARCH_TIMER_ISTATUS   (1 << 2)
 

Typedefs

typedef VOID(* CACHE_OPERATION )(VOID)
 
typedef VOID(* LINE_OPERATION )(UINTN)
 

Enumerations

enum  ARM_MEMORY_REGION_ATTRIBUTES {
  ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0, ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED, ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK, ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,
  ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE, ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE, ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH, ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,
  ARM_MEMORY_REGION_ATTRIBUTE_DEVICE, ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
}
 
enum  ARM_PROCESSOR_MODE {
  ARM_PROCESSOR_MODE_USER = 0x10, ARM_PROCESSOR_MODE_FIQ = 0x11, ARM_PROCESSOR_MODE_IRQ = 0x12, ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,
  ARM_PROCESSOR_MODE_ABORT = 0x17, ARM_PROCESSOR_MODE_HYP = 0x1A, ARM_PROCESSOR_MODE_UNDEFINED = 0x1B, ARM_PROCESSOR_MODE_SYSTEM = 0x1F,
  ARM_PROCESSOR_MODE_MASK = 0x1F
}
 

Functions

UINTN ReadCCSIDR (IN UINT32 CSSELR)
 
UINT32 ReadCCSIDR2 (IN UINT32 CSSELR)
 
UINT32 ReadCLIDR (VOID)
 
UINTN EFIAPI ArmDataCacheLineLength (VOID)
 
UINTN EFIAPI ArmInstructionCacheLineLength (VOID)
 
UINTN EFIAPI ArmCacheWritebackGranule (VOID)
 
UINTN EFIAPI ArmIsArchTimerImplemented (VOID)
 
UINTN EFIAPI ArmCacheInfo (VOID)
 
BOOLEAN EFIAPI ArmIsMpCore (VOID)
 
VOID EFIAPI ArmInvalidateDataCache (VOID)
 
VOID EFIAPI ArmCleanInvalidateDataCache (VOID)
 
VOID EFIAPI ArmCleanDataCache (VOID)
 
VOID EFIAPI ArmInvalidateInstructionCache (VOID)
 
VOID EFIAPI ArmInvalidateDataCacheEntryByMVA (IN UINTN Address)
 
VOID EFIAPI ArmCleanDataCacheEntryToPoUByMVA (IN UINTN Address)
 
VOID EFIAPI ArmInvalidateInstructionCacheEntryToPoUByMVA (IN UINTN Address)
 
VOID EFIAPI ArmCleanDataCacheEntryByMVA (IN UINTN Address)
 
VOID EFIAPI ArmCleanInvalidateDataCacheEntryByMVA (IN UINTN Address)
 
VOID EFIAPI ArmEnableDataCache (VOID)
 
VOID EFIAPI ArmDisableDataCache (VOID)
 
VOID EFIAPI ArmEnableInstructionCache (VOID)
 
VOID EFIAPI ArmDisableInstructionCache (VOID)
 
VOID EFIAPI ArmEnableMmu (VOID)
 
VOID EFIAPI ArmDisableMmu (VOID)
 
VOID EFIAPI ArmEnableCachesAndMmu (VOID)
 
VOID EFIAPI ArmDisableCachesAndMmu (VOID)
 
VOID EFIAPI ArmEnableInterrupts (VOID)
 
UINTN EFIAPI ArmDisableInterrupts (VOID)
 
BOOLEAN EFIAPI ArmGetInterruptState (VOID)
 
VOID EFIAPI ArmEnableAsynchronousAbort (VOID)
 
UINTN EFIAPI ArmDisableAsynchronousAbort (VOID)
 
VOID EFIAPI ArmEnableIrq (VOID)
 
UINTN EFIAPI ArmDisableIrq (VOID)
 
VOID EFIAPI ArmEnableFiq (VOID)
 
UINTN EFIAPI ArmDisableFiq (VOID)
 
BOOLEAN EFIAPI ArmGetFiqState (VOID)
 
VOID EFIAPI ArmInvalidateTlb (VOID)
 
VOID EFIAPI ArmUpdateTranslationTableEntry (IN VOID *TranslationTableEntry, IN VOID *Mva)
 
VOID EFIAPI ArmSetDomainAccessControl (IN UINT32 Domain)
 
VOID EFIAPI ArmSetTTBR0 (IN VOID *TranslationTableBase)
 
VOID EFIAPI ArmSetTTBCR (IN UINT32 Bits)
 
VOID *EFIAPI ArmGetTTBR0BaseAddress (VOID)
 
BOOLEAN EFIAPI ArmMmuEnabled (VOID)
 
VOID EFIAPI ArmEnableBranchPrediction (VOID)
 
VOID EFIAPI ArmDisableBranchPrediction (VOID)
 
VOID EFIAPI ArmSetLowVectors (VOID)
 
VOID EFIAPI ArmSetHighVectors (VOID)
 
VOID EFIAPI ArmDataMemoryBarrier (VOID)
 
VOID EFIAPI ArmDataSynchronizationBarrier (VOID)
 
VOID EFIAPI ArmInstructionSynchronizationBarrier (VOID)
 
VOID EFIAPI ArmWriteVBar (IN UINTN VectorBase)
 
UINTN EFIAPI ArmReadVBar (VOID)
 
VOID EFIAPI ArmWriteAuxCr (IN UINT32 Bit)
 
UINT32 EFIAPI ArmReadAuxCr (VOID)
 
VOID EFIAPI ArmSetAuxCrBit (IN UINT32 Bits)
 
VOID EFIAPI ArmUnsetAuxCrBit (IN UINT32 Bits)
 
VOID EFIAPI ArmCallSEV (VOID)
 
VOID EFIAPI ArmCallWFE (VOID)
 
VOID EFIAPI ArmCallWFI (VOID)
 
UINTN EFIAPI ArmReadMpidr (VOID)
 
UINTN EFIAPI ArmReadMidr (VOID)
 
UINT32 EFIAPI ArmReadCpacr (VOID)
 
VOID EFIAPI ArmWriteCpacr (IN UINT32 Access)
 
VOID EFIAPI ArmEnableVFP (VOID)
 
UINT32 EFIAPI ArmReadScr (VOID)
 
VOID EFIAPI ArmWriteScr (IN UINT32 Value)
 
UINT32 EFIAPI ArmReadMVBar (VOID)
 
VOID EFIAPI ArmWriteMVBar (IN UINT32 VectorMonitorBase)
 
UINT32 EFIAPI ArmReadSctlr (VOID)
 
VOID EFIAPI ArmWriteSctlr (IN UINT32 Value)
 
UINTN EFIAPI ArmReadHVBar (VOID)
 
VOID EFIAPI ArmWriteHVBar (IN UINTN HypModeVectorBase)
 
UINTN EFIAPI ArmReadCpuActlr (VOID)
 
VOID EFIAPI ArmWriteCpuActlr (IN UINTN Val)
 
VOID EFIAPI ArmSetCpuActlrBit (IN UINTN Bits)
 
VOID EFIAPI ArmUnsetCpuActlrBit (IN UINTN Bits)
 
UINTN EFIAPI ArmReadCntFrq (VOID)
 
VOID EFIAPI ArmWriteCntFrq (UINTN FreqInHz)
 
UINT64 EFIAPI ArmReadCntPct (VOID)
 
UINTN EFIAPI ArmReadCntkCtl (VOID)
 
VOID EFIAPI ArmWriteCntkCtl (UINTN Val)
 
UINTN EFIAPI ArmReadCntpTval (VOID)
 
VOID EFIAPI ArmWriteCntpTval (UINTN Val)
 
UINTN EFIAPI ArmReadCntpCtl (VOID)
 
VOID EFIAPI ArmWriteCntpCtl (UINTN Val)
 
UINTN EFIAPI ArmReadCntvTval (VOID)
 
VOID EFIAPI ArmWriteCntvTval (UINTN Val)
 
UINTN EFIAPI ArmReadCntvCtl (VOID)
 
VOID EFIAPI ArmWriteCntvCtl (UINTN Val)
 
UINT64 EFIAPI ArmReadCntvCt (VOID)
 
UINT64 EFIAPI ArmReadCntpCval (VOID)
 
VOID EFIAPI ArmWriteCntpCval (UINT64 Val)
 
UINT64 EFIAPI ArmReadCntvCval (VOID)
 
VOID EFIAPI ArmWriteCntvCval (UINT64 Val)
 
UINT64 EFIAPI ArmReadCntvOff (VOID)
 
VOID EFIAPI ArmWriteCntvOff (UINT64 Val)
 
UINTN EFIAPI ArmGetPhysicalAddressBits (VOID)
 
BOOLEAN EFIAPI ArmHasGicSystemRegisters (VOID)
 
BOOLEAN EFIAPI ArmHasCcidx (VOID)
 
BOOLEAN EFIAPI ArmHasSecurityExtensions (VOID)
 

Detailed Description

Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.
Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.

SPDX-License-Identifier: BSD-2-Clause-Patent

Macro Definition Documentation

#define ARM_ARCH_TIMER_ENABLE   (1 << 0)
#define ARM_ARCH_TIMER_IMASK   (1 << 1)
#define ARM_ARCH_TIMER_ISTATUS   (1 << 2)
#define ARM_CLUSTER_MASK   ARM_CORE_AFF1
#define ARM_CORE_AFF0   0xFF
#define ARM_CORE_AFF1   (0xFF << 8)
#define ARM_CORE_AFF2   (0xFF << 16)
#define ARM_CORE_AFF3   (0xFFULL << 32)
#define ARM_CORE_MASK   ARM_CORE_AFF0
#define ARM_CPU_IMPLEMENTER_ARMLTD   (0x41U << 24)
#define ARM_CPU_IMPLEMENTER_DEC   (0x44U << 24)
#define ARM_CPU_IMPLEMENTER_MARVELL   (0x56U << 24)
#define ARM_CPU_IMPLEMENTER_MASK   (0xFFU << 24)
#define ARM_CPU_IMPLEMENTER_MOT   (0x4DU << 24)
#define ARM_CPU_IMPLEMENTER_QUALCOMM   (0x51U << 24)
#define ARM_CPU_PRIMARY_PART_CORTEXA15   (0xC0F << 4)
#define ARM_CPU_PRIMARY_PART_CORTEXA5   (0xC05 << 4)
#define ARM_CPU_PRIMARY_PART_CORTEXA7   (0xC07 << 4)
#define ARM_CPU_PRIMARY_PART_CORTEXA8   (0xC08 << 4)
#define ARM_CPU_PRIMARY_PART_CORTEXA9   (0xC09 << 4)
#define ARM_CPU_PRIMARY_PART_MASK   (0xFFF << 4)
#define EFI_MEMORY_CACHETYPE_MASK
Value:
(EFI_MEMORY_UC | EFI_MEMORY_WC | \
EFI_MEMORY_WT | EFI_MEMORY_WB | \
EFI_MEMORY_UCE)
#define GET_CLUSTER_ID (   MpId)    (((MpId) & ARM_CLUSTER_MASK) >> 8)
#define GET_CORE_ID (   MpId)    ((MpId) & ARM_CORE_MASK)
#define GET_MPID (   ClusterId,
  CoreId 
)    (((ClusterId) << 8) | (CoreId))
#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE (   attr)    ((UINT32)(attr) & 1)
#define PRIMARY_CORE_ID   (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)

Typedef Documentation

typedef VOID(* CACHE_OPERATION)(VOID)
typedef VOID(* LINE_OPERATION)(UINTN)

Enumeration Type Documentation

enum ARM_MEMORY_REGION_ATTRIBUTES

The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.

The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only be used in Secure World to distinguished Secure to Non-Secure memory.

Enumerator
ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED 
ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED 
ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK 
ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK 
ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE 
ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE 
ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH 
ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH 
ARM_MEMORY_REGION_ATTRIBUTE_DEVICE 
ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE 
enum ARM_PROCESSOR_MODE
Enumerator
ARM_PROCESSOR_MODE_USER 
ARM_PROCESSOR_MODE_FIQ 
ARM_PROCESSOR_MODE_IRQ 
ARM_PROCESSOR_MODE_SUPERVISOR 
ARM_PROCESSOR_MODE_ABORT 
ARM_PROCESSOR_MODE_HYP 
ARM_PROCESSOR_MODE_UNDEFINED 
ARM_PROCESSOR_MODE_SYSTEM 
ARM_PROCESSOR_MODE_MASK 

Function Documentation

UINTN EFIAPI ArmCacheInfo ( VOID  )
UINTN EFIAPI ArmCacheWritebackGranule ( VOID  )
VOID EFIAPI ArmCallSEV ( VOID  )
VOID EFIAPI ArmCallWFE ( VOID  )
VOID EFIAPI ArmCallWFI ( VOID  )
VOID EFIAPI ArmCleanDataCache ( VOID  )
VOID EFIAPI ArmCleanDataCacheEntryByMVA ( IN UINTN  Address)
VOID EFIAPI ArmCleanDataCacheEntryToPoUByMVA ( IN UINTN  Address)
VOID EFIAPI ArmCleanInvalidateDataCache ( VOID  )
VOID EFIAPI ArmCleanInvalidateDataCacheEntryByMVA ( IN UINTN  Address)
UINTN EFIAPI ArmDataCacheLineLength ( VOID  )
VOID EFIAPI ArmDataMemoryBarrier ( VOID  )
VOID EFIAPI ArmDataSynchronizationBarrier ( VOID  )
UINTN EFIAPI ArmDisableAsynchronousAbort ( VOID  )
VOID EFIAPI ArmDisableBranchPrediction ( VOID  )
VOID EFIAPI ArmDisableCachesAndMmu ( VOID  )
VOID EFIAPI ArmDisableDataCache ( VOID  )
UINTN EFIAPI ArmDisableFiq ( VOID  )
VOID EFIAPI ArmDisableInstructionCache ( VOID  )
UINTN EFIAPI ArmDisableInterrupts ( VOID  )
UINTN EFIAPI ArmDisableIrq ( VOID  )
VOID EFIAPI ArmDisableMmu ( VOID  )
VOID EFIAPI ArmEnableAsynchronousAbort ( VOID  )
VOID EFIAPI ArmEnableBranchPrediction ( VOID  )
VOID EFIAPI ArmEnableCachesAndMmu ( VOID  )
VOID EFIAPI ArmEnableDataCache ( VOID  )
VOID EFIAPI ArmEnableFiq ( VOID  )
VOID EFIAPI ArmEnableInstructionCache ( VOID  )
VOID EFIAPI ArmEnableInterrupts ( VOID  )
VOID EFIAPI ArmEnableIrq ( VOID  )
VOID EFIAPI ArmEnableMmu ( VOID  )
VOID EFIAPI ArmEnableVFP ( VOID  )
BOOLEAN EFIAPI ArmGetFiqState ( VOID  )
BOOLEAN EFIAPI ArmGetInterruptState ( VOID  )
UINTN EFIAPI ArmGetPhysicalAddressBits ( VOID  )
VOID* EFIAPI ArmGetTTBR0BaseAddress ( VOID  )
BOOLEAN EFIAPI ArmHasCcidx ( VOID  )

Checks if CCIDX is implemented.

Return values
TRUECCIDX is implemented.
FALSECCIDX is not implemented.
BOOLEAN EFIAPI ArmHasGicSystemRegisters ( VOID  )

ID Register Helper functions Check whether the CPU supports the GIC system register interface (any version)

Returns
Whether GIC System Register Interface is supported
BOOLEAN EFIAPI ArmHasSecurityExtensions ( VOID  )

AArch32-only ID Register Helper functions Check whether the CPU supports the Security extensions

Returns
Whether the Security extensions are implemented
UINTN EFIAPI ArmInstructionCacheLineLength ( VOID  )
VOID EFIAPI ArmInstructionSynchronizationBarrier ( VOID  )
VOID EFIAPI ArmInvalidateDataCache ( VOID  )
VOID EFIAPI ArmInvalidateDataCacheEntryByMVA ( IN UINTN  Address)
VOID EFIAPI ArmInvalidateInstructionCache ( VOID  )
VOID EFIAPI ArmInvalidateInstructionCacheEntryToPoUByMVA ( IN UINTN  Address)
VOID EFIAPI ArmInvalidateTlb ( VOID  )

Invalidate Data and Instruction TLBs

UINTN EFIAPI ArmIsArchTimerImplemented ( VOID  )
BOOLEAN EFIAPI ArmIsMpCore ( VOID  )
BOOLEAN EFIAPI ArmMmuEnabled ( VOID  )
UINT32 EFIAPI ArmReadAuxCr ( VOID  )
UINTN EFIAPI ArmReadCntFrq ( VOID  )
UINTN EFIAPI ArmReadCntkCtl ( VOID  )
UINT64 EFIAPI ArmReadCntPct ( VOID  )
UINTN EFIAPI ArmReadCntpCtl ( VOID  )
UINT64 EFIAPI ArmReadCntpCval ( VOID  )
UINTN EFIAPI ArmReadCntpTval ( VOID  )
UINT64 EFIAPI ArmReadCntvCt ( VOID  )
UINTN EFIAPI ArmReadCntvCtl ( VOID  )
UINT64 EFIAPI ArmReadCntvCval ( VOID  )
UINT64 EFIAPI ArmReadCntvOff ( VOID  )
UINTN EFIAPI ArmReadCntvTval ( VOID  )
UINT32 EFIAPI ArmReadCpacr ( VOID  )
UINTN EFIAPI ArmReadCpuActlr ( VOID  )
UINTN EFIAPI ArmReadHVBar ( VOID  )
UINTN EFIAPI ArmReadMidr ( VOID  )
UINTN EFIAPI ArmReadMpidr ( VOID  )
UINT32 EFIAPI ArmReadMVBar ( VOID  )
UINT32 EFIAPI ArmReadScr ( VOID  )

Get the Secure Configuration Register value

Returns
Value read from the Secure Configuration Register
UINT32 EFIAPI ArmReadSctlr ( VOID  )
UINTN EFIAPI ArmReadVBar ( VOID  )
VOID EFIAPI ArmSetAuxCrBit ( IN UINT32  Bits)
VOID EFIAPI ArmSetCpuActlrBit ( IN UINTN  Bits)
VOID EFIAPI ArmSetDomainAccessControl ( IN UINT32  Domain)
VOID EFIAPI ArmSetHighVectors ( VOID  )
VOID EFIAPI ArmSetLowVectors ( VOID  )
VOID EFIAPI ArmSetTTBCR ( IN UINT32  Bits)
VOID EFIAPI ArmSetTTBR0 ( IN VOID *  TranslationTableBase)
VOID EFIAPI ArmUnsetAuxCrBit ( IN UINT32  Bits)
VOID EFIAPI ArmUnsetCpuActlrBit ( IN UINTN  Bits)
VOID EFIAPI ArmUpdateTranslationTableEntry ( IN VOID *  TranslationTableEntry,
IN VOID *  Mva 
)
VOID EFIAPI ArmWriteAuxCr ( IN UINT32  Bit)
VOID EFIAPI ArmWriteCntFrq ( UINTN  FreqInHz)
VOID EFIAPI ArmWriteCntkCtl ( UINTN  Val)
VOID EFIAPI ArmWriteCntpCtl ( UINTN  Val)
VOID EFIAPI ArmWriteCntpCval ( UINT64  Val)
VOID EFIAPI ArmWriteCntpTval ( UINTN  Val)
VOID EFIAPI ArmWriteCntvCtl ( UINTN  Val)
VOID EFIAPI ArmWriteCntvCval ( UINT64  Val)
VOID EFIAPI ArmWriteCntvOff ( UINT64  Val)
VOID EFIAPI ArmWriteCntvTval ( UINTN  Val)
VOID EFIAPI ArmWriteCpacr ( IN UINT32  Access)
VOID EFIAPI ArmWriteCpuActlr ( IN UINTN  Val)
VOID EFIAPI ArmWriteHVBar ( IN UINTN  HypModeVectorBase)
VOID EFIAPI ArmWriteMVBar ( IN UINT32  VectorMonitorBase)
VOID EFIAPI ArmWriteScr ( IN UINT32  Value)

Set the Secure Configuration Register

Parameters
ValueValue to write to the Secure Configuration Register
VOID EFIAPI ArmWriteSctlr ( IN UINT32  Value)
VOID EFIAPI ArmWriteVBar ( IN UINTN  VectorBase)
UINTN ReadCCSIDR ( IN UINT32  CSSELR)

Reads the CCSIDR register for the specified cache.

Parameters
CSSELRThe CSSELR cache selection register value.
Returns
The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode. Returns the contents of the CCSIDR register in AARCH32 mode.
UINT32 ReadCCSIDR2 ( IN UINT32  CSSELR)

Reads the CCSIDR2 for the specified cache.

Parameters
CSSELRThe CSSELR cache selection register value
Returns
The contents of the CCSIDR2 register for the specified cache.
UINT32 ReadCLIDR ( VOID  )

Reads the Cache Level ID (CLIDR) register.

Returns
The contents of the CLIDR_EL1 register.