ArmGicLib.h File Reference

Macros
#define	ARM_GIC_ICDDCR   0x000
#define	ARM_GIC_ICDICTR   0x004
#define	ARM_GIC_ICDIIDR   0x008
#define	ARM_GIC_ICDISR   0x080
#define	ARM_GIC_ICDISER   0x100
#define	ARM_GIC_ICDICER   0x180
#define	ARM_GIC_ICDSPR   0x200
#define	ARM_GIC_ICDICPR   0x280
#define	ARM_GIC_ICDABR   0x300
#define	ARM_GIC_ICDIPR   0x400
#define	ARM_GIC_ICDIPTR   0x800
#define	ARM_GIC_ICDICFR   0xC00
#define	ARM_GIC_ICDPPISR   0xD00
#define	ARM_GIC_ICDSGIR   0xF00
#define	ARM_GICD_IROUTER   0x6100
#define	ARM_GIC_ICDDCR_ARE   (1 << 4)
#define	ARM_GIC_ICDDCR_DS   (1 << 6)
#define	ARM_GIC_ICDICFR_WIDTH   32
#define	ARM_GIC_ICDICFR_BYTES   (ARM_GIC_ICDICFR_WIDTH / 8)
#define	ARM_GIC_ICDICFR_F_WIDTH   2
#define	ARM_GIC_ICDICFR_F_STRIDE   16
#define	ARM_GIC_ICDICFR_F_CONFIG1_BIT   1
#define	ARM_GIC_ICDICFR_LEVEL_TRIGGERED   0x0
#define	ARM_GIC_ICDICFR_EDGE_TRIGGERED   0x1
#define	ARM_GICR_CTLR_FRAME_SIZE   SIZE_64KB
#define	ARM_GICR_SGI_PPI_FRAME_SIZE   SIZE_64KB
#define	ARM_GICR_SGI_VLPI_FRAME_SIZE   SIZE_64KB
#define	ARM_GICR_SGI_RESERVED_FRAME_SIZE   SIZE_64KB
#define	ARM_GICR_TYPER   0x0008
#define	ARM_GICR_TYPER_PLPIS   (1 << 0)
#define	ARM_GICR_TYPER_VLPIS   (1 << 1)
#define	ARM_GICR_TYPER_DIRECTLPI   (1 << 3)
#define	ARM_GICR_TYPER_LAST   (1 << 4)
#define	ARM_GICR_TYPER_DPGS   (1 << 5)
#define	ARM_GICR_TYPER_PROCNO   (0xFFFF << 8)
#define	ARM_GICR_TYPER_COMMONLPIAFF   (0x3 << 24)
#define	ARM_GICR_TYPER_AFFINITY   (0xFFFFFFFFULL << 32)
#define	ARM_GICR_TYPER_GET_AFFINITY(TypeReg)
#define	ARM_GICR_ISENABLER   0x0100
#define	ARM_GICR_ICENABLER   0x0180
#define	ARM_GIC_ICCICR   0x00
#define	ARM_GIC_ICCPMR   0x04
#define	ARM_GIC_ICCBPR   0x08
#define	ARM_GIC_ICCIAR   0x0C
#define	ARM_GIC_ICCEIOR   0x10
#define	ARM_GIC_ICCRPR   0x14
#define	ARM_GIC_ICCPIR   0x18
#define	ARM_GIC_ICCABPR   0x1C
#define	ARM_GIC_ICCIIDR   0xFC
#define	ARM_GIC_ICDSGIR_FILTER_TARGETLIST   0x0
#define	ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE   0x1
#define	ARM_GIC_ICDSGIR_FILTER_ITSELF   0x2
#define	ARM_GIC_ICCICR_ENABLE_SECURE   0x01
#define	ARM_GIC_ICCICR_ENABLE_NS   0x02
#define	ARM_GIC_ICCICR_ACK_CTL   0x04
#define	ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ   0x08
#define	ARM_GIC_ICCICR_USE_SBPR   0x10
#define	ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr)   (((IccIidr) >> 20) & 0xFFF)
#define	ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr)   (((IccIidr) >> 16) & 0xF)
#define	ARM_GIC_ICCIIDR_GET_REVISION(IccIidr)   (((IccIidr) >> 12) & 0xF)
#define	ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr)   ((IccIidr) & 0xFFF)
#define	ARM_GIC_ICCIAR_ACKINTID   0x3FF
#define	ARM_GIC_IS_SPECIAL_INTERRUPTS(Interrupt)   (((Interrupt) >= 1020) && ((Interrupt) <= 1023))
#define	ICC_SRE_EL2_SRE   (1 << 0)
#define	ARM_GICD_IROUTER_IRM   BIT31

Functions
UINTN EFIAPI	ArmGicGetInterfaceIdentification (IN INTN GicInterruptInterfaceBase)
VOID EFIAPI	ArmGicSetupNonSecure (IN UINTN MpId, IN INTN GicDistributorBase, IN INTN GicInterruptInterfaceBase)
VOID EFIAPI	ArmGicSetSecureInterrupts (IN UINTN GicDistributorBase, IN UINTN *GicSecureInterruptMask, IN UINTN GicSecureInterruptMaskSize)
VOID EFIAPI	ArmGicEnableInterruptInterface (IN INTN GicInterruptInterfaceBase)
VOID EFIAPI	ArmGicDisableInterruptInterface (IN INTN GicInterruptInterfaceBase)
VOID EFIAPI	ArmGicEnableDistributor (IN INTN GicDistributorBase)
VOID EFIAPI	ArmGicDisableDistributor (IN INTN GicDistributorBase)
UINTN EFIAPI	ArmGicGetMaxNumInterrupts (IN INTN GicDistributorBase)
VOID EFIAPI	ArmGicSendSgiTo (IN INTN GicDistributorBase, IN INTN TargetListFilter, IN INTN CPUTargetList, IN INTN SgiId)
UINTN EFIAPI	ArmGicAcknowledgeInterrupt (IN UINTN GicInterruptInterfaceBase, OUT UINTN *InterruptId)
VOID EFIAPI	ArmGicEndOfInterrupt (IN UINTN GicInterruptInterfaceBase, IN UINTN Source)
UINTN EFIAPI	ArmGicSetPriorityMask (IN INTN GicInterruptInterfaceBase, IN INTN PriorityMask)
VOID EFIAPI	ArmGicSetInterruptPriority (IN UINTN GicDistributorBase, IN UINTN GicRedistributorBase, IN UINTN Source, IN UINTN Priority)
VOID EFIAPI	ArmGicEnableInterrupt (IN UINTN GicDistributorBase, IN UINTN GicRedistributorBase, IN UINTN Source)
VOID EFIAPI	ArmGicDisableInterrupt (IN UINTN GicDistributorBase, IN UINTN GicRedistributorBase, IN UINTN Source)
BOOLEAN EFIAPI	ArmGicIsInterruptEnabled (IN UINTN GicDistributorBase, IN UINTN GicRedistributorBase, IN UINTN Source)
VOID EFIAPI	ArmGicV2SetupNonSecure (IN UINTN MpId, IN INTN GicDistributorBase, IN INTN GicInterruptInterfaceBase)
VOID EFIAPI	ArmGicV2EnableInterruptInterface (IN INTN GicInterruptInterfaceBase)
VOID EFIAPI	ArmGicV2DisableInterruptInterface (IN INTN GicInterruptInterfaceBase)
UINTN EFIAPI	ArmGicV2AcknowledgeInterrupt (IN UINTN GicInterruptInterfaceBase)
VOID EFIAPI	ArmGicV2EndOfInterrupt (IN UINTN GicInterruptInterfaceBase, IN UINTN Source)
UINT32 EFIAPI	ArmGicV3GetControlSystemRegisterEnable (VOID)
VOID EFIAPI	ArmGicV3SetControlSystemRegisterEnable (IN UINT32 ControlSystemRegisterEnable)
VOID EFIAPI	ArmGicV3EnableInterruptInterface (VOID)
VOID EFIAPI	ArmGicV3DisableInterruptInterface (VOID)
UINTN EFIAPI	ArmGicV3AcknowledgeInterrupt (VOID)
VOID EFIAPI	ArmGicV3EndOfInterrupt (IN UINTN Source)
VOID	ArmGicV3SetBinaryPointer (IN UINTN BinaryPoint)
VOID	ArmGicV3SetPriorityMask (IN UINTN Priority)

Detailed Description

Copyright (c) 2011-2021, Arm Limited. All rights reserved.

SPDX-License-Identifier: BSD-2-Clause-Patent

Macro Definition Documentation

#define ARM_GIC_ICCABPR   0x1C

#define ARM_GIC_ICCBPR   0x08

#define ARM_GIC_ICCEIOR   0x10

#define ARM_GIC_ICCIAR   0x0C

#define ARM_GIC_ICCIAR_ACKINTID   0x3FF

#define ARM_GIC_ICCICR   0x00

#define ARM_GIC_ICCICR_ACK_CTL   0x04

#define ARM_GIC_ICCICR_ENABLE_NS   0x02

#define ARM_GIC_ICCICR_ENABLE_SECURE   0x01

#define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ   0x08

#define ARM_GIC_ICCICR_USE_SBPR   0x10

#define ARM_GIC_ICCIIDR   0xFC

#define ARM_GIC_ICCIIDR_GET_ARCH_VERSION

(

IccIidr

)

(((IccIidr) >> 16) & 0xF)

#define ARM_GIC_ICCIIDR_GET_IMPLEMENTER

(

IccIidr

)

((IccIidr) & 0xFFF)

#define ARM_GIC_ICCIIDR_GET_PRODUCT_ID

(

IccIidr

)

(((IccIidr) >> 20) & 0xFFF)

#define ARM_GIC_ICCIIDR_GET_REVISION

(

IccIidr

)

(((IccIidr) >> 12) & 0xF)

#define ARM_GIC_ICCPIR   0x18

#define ARM_GIC_ICCPMR   0x04

#define ARM_GIC_ICCRPR   0x14

#define ARM_GIC_ICDABR   0x300

#define ARM_GIC_ICDDCR   0x000

#define ARM_GIC_ICDDCR_ARE   (1 << 4)

#define ARM_GIC_ICDDCR_DS   (1 << 6)

#define ARM_GIC_ICDICER   0x180

#define ARM_GIC_ICDICFR   0xC00

#define ARM_GIC_ICDICFR_BYTES   (ARM_GIC_ICDICFR_WIDTH / 8)

#define ARM_GIC_ICDICFR_EDGE_TRIGGERED   0x1

#define ARM_GIC_ICDICFR_F_CONFIG1_BIT   1

#define ARM_GIC_ICDICFR_F_STRIDE   16

#define ARM_GIC_ICDICFR_F_WIDTH   2

#define ARM_GIC_ICDICFR_LEVEL_TRIGGERED   0x0

#define ARM_GIC_ICDICFR_WIDTH   32

#define ARM_GIC_ICDICPR   0x280

#define ARM_GIC_ICDICTR   0x004

#define ARM_GIC_ICDIIDR   0x008

#define ARM_GIC_ICDIPR   0x400

#define ARM_GIC_ICDIPTR   0x800

#define ARM_GIC_ICDISER   0x100

#define ARM_GIC_ICDISR   0x080

#define ARM_GIC_ICDPPISR   0xD00

#define ARM_GIC_ICDSGIR   0xF00

#define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE   0x1

#define ARM_GIC_ICDSGIR_FILTER_ITSELF   0x2

#define ARM_GIC_ICDSGIR_FILTER_TARGETLIST   0x0

#define ARM_GIC_ICDSPR   0x200

#define ARM_GIC_IS_SPECIAL_INTERRUPTS

(

Interrupt

)

(((Interrupt) >= 1020) && ((Interrupt) <= 1023))

#define ARM_GICD_IROUTER   0x6100

#define ARM_GICD_IROUTER_IRM   BIT31

#define ARM_GICR_CTLR_FRAME_SIZE   SIZE_64KB

#define ARM_GICR_ICENABLER   0x0180

#define ARM_GICR_ISENABLER   0x0100

#define ARM_GICR_SGI_PPI_FRAME_SIZE   SIZE_64KB

#define ARM_GICR_SGI_RESERVED_FRAME_SIZE   SIZE_64KB

#define ARM_GICR_SGI_VLPI_FRAME_SIZE   SIZE_64KB

#define ARM_GICR_TYPER   0x0008

#define ARM_GICR_TYPER_AFFINITY   (0xFFFFFFFFULL << 32)

#define ARM_GICR_TYPER_COMMONLPIAFF   (0x3 << 24)

#define ARM_GICR_TYPER_DIRECTLPI   (1 << 3)

#define ARM_GICR_TYPER_DPGS   (1 << 5)

#define ARM_GICR_TYPER_GET_AFFINITY

(

TypeReg

)

Value:

(((TypeReg) & \
                                                ARM_GICR_TYPER_AFFINITY) >> 32)

#define ARM_GICR_TYPER_LAST   (1 << 4)

#define ARM_GICR_TYPER_PLPIS   (1 << 0)

#define ARM_GICR_TYPER_PROCNO   (0xFFFF << 8)

#define ARM_GICR_TYPER_VLPIS   (1 << 1)

#define ICC_SRE_EL2_SRE   (1 << 0)

Function Documentation

UINTN EFIAPI ArmGicAcknowledgeInterrupt	(	IN UINTN	GicInterruptInterfaceBase,
		OUT UINTN *	InterruptId
	)

VOID EFIAPI ArmGicDisableDistributor

(

IN INTN

GicDistributorBase

)

VOID EFIAPI ArmGicDisableInterrupt	(	IN UINTN	GicDistributorBase,
		IN UINTN	GicRedistributorBase,
		IN UINTN	Source
	)

VOID EFIAPI ArmGicDisableInterruptInterface

(

IN INTN

GicInterruptInterfaceBase

)

VOID EFIAPI ArmGicEnableDistributor

(

IN INTN

GicDistributorBase

)

VOID EFIAPI ArmGicEnableInterrupt	(	IN UINTN	GicDistributorBase,
		IN UINTN	GicRedistributorBase,
		IN UINTN	Source
	)

VOID EFIAPI ArmGicEnableInterruptInterface

(

IN INTN

GicInterruptInterfaceBase

)

VOID EFIAPI ArmGicEndOfInterrupt	(	IN UINTN	GicInterruptInterfaceBase,
		IN UINTN	Source
	)

UINTN EFIAPI ArmGicGetInterfaceIdentification

(

IN INTN

GicInterruptInterfaceBase

)

UINTN EFIAPI ArmGicGetMaxNumInterrupts

(

IN INTN

GicDistributorBase

)

BOOLEAN EFIAPI ArmGicIsInterruptEnabled	(	IN UINTN	GicDistributorBase,
		IN UINTN	GicRedistributorBase,
		IN UINTN	Source
	)

VOID EFIAPI ArmGicSendSgiTo	(	IN INTN	GicDistributorBase,
		IN INTN	TargetListFilter,
		IN INTN	CPUTargetList,
		IN INTN	SgiId
	)

VOID EFIAPI ArmGicSetInterruptPriority	(	IN UINTN	GicDistributorBase,
		IN UINTN	GicRedistributorBase,
		IN UINTN	Source,
		IN UINTN	Priority
	)

UINTN EFIAPI ArmGicSetPriorityMask	(	IN INTN	GicInterruptInterfaceBase,
		IN INTN	PriorityMask
	)

VOID EFIAPI ArmGicSetSecureInterrupts	(	IN UINTN	GicDistributorBase,
		IN UINTN *	GicSecureInterruptMask,
		IN UINTN	GicSecureInterruptMaskSize
	)

VOID EFIAPI ArmGicSetupNonSecure	(	IN UINTN	MpId,
		IN INTN	GicDistributorBase,
		IN INTN	GicInterruptInterfaceBase
	)

UINTN EFIAPI ArmGicV2AcknowledgeInterrupt

(

IN UINTN

GicInterruptInterfaceBase

)

VOID EFIAPI ArmGicV2DisableInterruptInterface

(

IN INTN

GicInterruptInterfaceBase

)

VOID EFIAPI ArmGicV2EnableInterruptInterface

(

IN INTN

GicInterruptInterfaceBase

)

VOID EFIAPI ArmGicV2EndOfInterrupt	(	IN UINTN	GicInterruptInterfaceBase,
		IN UINTN	Source
	)

VOID EFIAPI ArmGicV2SetupNonSecure	(	IN UINTN	MpId,
		IN INTN	GicDistributorBase,
		IN INTN	GicInterruptInterfaceBase
	)

UINTN EFIAPI ArmGicV3AcknowledgeInterrupt

(

VOID

)

VOID EFIAPI ArmGicV3DisableInterruptInterface

(

VOID

)

VOID EFIAPI ArmGicV3EnableInterruptInterface

(

VOID

)

VOID EFIAPI ArmGicV3EndOfInterrupt

(

IN UINTN

Source

)

UINT32 EFIAPI ArmGicV3GetControlSystemRegisterEnable

(

VOID

)

VOID ArmGicV3SetBinaryPointer

(

IN UINTN

BinaryPoint

)

VOID EFIAPI ArmGicV3SetControlSystemRegisterEnable

(

IN UINT32

ControlSystemRegisterEnable

)

VOID ArmGicV3SetPriorityMask

(

IN UINTN

Priority

)